stuck-on fault

См. также в других словарях:

• Stuck-at fault — A Stuck at fault is a particular fault model used by fault simulators and Automatic test pattern generation (ATPG) tools to mimic a manufacturing defect within an integrated circuit. Individual signals and pins are assumed to be stuck at Logical… …   Wikipedia

• Fault coverage — refers to the percentage of some type of fault that can be detected during the test of an electronic system, usually an integrated circuit. High fault coverage is particularly valuable during manufacturing test, and techniques such as Design For… …   Wikipedia

• Fault model — A fault model is an engineering model of something that could go wrong in the construction or operation of a piece of equipment. From the model, the designer or user can then predict the consequences of this particular fault. Fault models can be… …   Wikipedia

• Fault friction — describes the relation of friction to fault mechanics. Rock failure and associated earthquakes are very much a fractal operation (see Characteristic earthquakes). The process remains scale invariant down to the smallest crystal. Thus, the… …   Wikipedia

• Single Stuck Line — is a fault model used in digital circuits. It is used for post manufacturing testing, not design testing. The model assumes one line or node in the digital circuit is stuck at logic high or logic low. When a line is stuck it is called a fault.… …   Wikipedia

• Semiconductor fault diagnostics — are predictive software algorithms which are used to refine and localize the circuitry responsible for the failure of scan based devices. [cite conference| last=Crowell| first=G| coauthors=Press, R.| title=Using Scan Based Techniques for Fault… …   Wikipedia

• Automatic test pattern generation — ATPG (acronym for both Automatic Test Pattern Generation and Automatic Test Pattern Generator) is an electronic design automation method/technology used to find an input (or test) sequence that, when applied to a digital circuit, enables testers… …   Wikipedia

• Modèle de faute — Les modèles de faute sont des abstractions utilisées pour modéliser une défaut accidentel dans un circuit électronique (numérique). Chaque type de modèle de faute peut correspondre à plusieurs origines physiques différentes. Cette représentation… …   Wikipédia en Français

• Iddq testing — is a method for testing CMOS integrated circuits for the presence of manufacturing faults. It relies on measuring the supply current (Idd) in the quiescent state (when the circuit is not switching and inputs are held at static values). The… …   Wikipedia

• ГОСТ Р 53195.5-2010: Безопасность функциональная связанных с безопасностью зданий и сооружений систем. Часть 5. Меры по снижению риска, методы оценки — Терминология ГОСТ Р 53195.5 2010: Безопасность функциональная связанных с безопасностью зданий и сооружений систем. Часть 5. Меры по снижению риска, методы оценки оригинал документа: 3.1 антивалентные сигналы (antivalent signals): Два сигнала с… …   Словарь-справочник терминов нормативно-технической документации

• Logic redundancy — occurs in a a digital gate network containing circuitry that does not affect the static logic function. There are several reasons why logic redundancy may exist. One reason is that it may have been added deliberately to suppress transient… …   Wikipedia